SAN JOSE, Calif., July 21, 1998 -- Allayer Communications today announced a chip that allows the design of Gigabit Ethernet switches with a port cost below $100. This advance is a four-fold improvement over the industry's current state-of-the-art which uses Application Specific Integrated Circuits (ASICs) to achieve a port cost of $400.

This breakthrough will accelerate the growth of the Gigabit Ethernet industry by making possible affordable, high-speed switches that eliminate bottlenecks in office networks, and provide faster and more reliable connections to servers. This advance will also make it possible for Gigabit switches to replace hundreds of thousands of slower 155 Mbps ATM switches in the Internet backbone.

The AL1000 contains all the digital circuitry needed to implement the switching function for two Gigabit Ethernet ports according to the IEEE802.3z standard. The full-duplex chip works with network management standards such as SNMP (Simple Network Management Protocol) and RMON (Remote Network Monitoring).

The new device uses the patent-pending 4 Gbps RoX (Ring of Switches) expansion bus to link multiple AL1000s and provide a scalable solution that allows engineers to design a 2, 4, 6 or 8 port switch (diagram 1). Based on network traffic calculations, the RoX bus achieves wire-speed transfers for 2 or 4 port Gigabit switches, and wire-speed transfers 90 percent of the time for 6 or 8 port switches. The RoX bus can connect an optional AL300 chip that collects network management information reported from each AL1000.

The RoX bus can also be used in a hybrid switch that allows the AL1000 to work closely with up to three of Allayer's AL100 Fast Ethernet switch chips (diagram 2). This architecture allows engineers to design a Fast Ethernet switch with two high-speed Gigabit ports that can funnel high volumes of data to other departments, backbones or servers.

The AL1000 contains all the digital circuits needed to implement a two port switching function (diagram 3). Two of the interfaces on the AL1000 connect to the SERDES devices that form the first layer of the physical interface. The AL1000 also has interfaces to the RoX bus that allows engineers to expand the number of ports in a switch, and interfaces to SGRAMs that buffer incoming and outgoing data.

According to David Wong, Director of Marketing, "We achieved our breakthrough design by bringing together a team of the industry's best integrated circuit (IC) engineers and switch designers. This combined expertise produced a powerful synergy that enabled them to rewrite the book of switch chip design.

"As an example, the IC engineers conceived the fast processing circuits that could keep up with the Gigabit speed. The switch designers conceived the high-speed, chip-to-chip RoX bus and an architecture that uses low-cost SGRAMs (Synchronous Graphic Random Access Memory) to do buffering."

Block Diagram Functions

The main interfaces on the device are the two Gigabit Media Access Controller (GMAC) ports that connect the AL1000 to the SERDES devices that form the first layer of the physical interface (diagram 4).

The AL1000 also manages two SGRAM (Synchronous Graphic Random Access Memory) interfaces that each support up to 512 Kbits X 32 bits of external memory. One SGRAM interface buffers the outgoing (and incoming) data for the Port 1 GMAC, and the second SGRAM interface buffers the data for Port 2.

The VLAN Tx/Rx buffer registers contain control logic that modifies the Tx/Rx packets with VLAN tag insertion, stripping and CRC regeneration. The SSRAM table update and packet control elements use an on-chip memory or an external SSRAM array (16Kbits X 36 bits) to do address learning, aging and destination address mapping.

Each Gigabit GMAC/PCS block is responsible for packet transmission and reception according to the IEEE802.3z standard. This block transfers data from incoming packets into the associated RX buffer, and transfers data from the appropriate TX buffer into the outgoing packets. The GMAC/PCS block also communicates with the Packet Queuing Control block and sends the IEEE802.3x flow control packets based on the packet queue status which eases congestion in the switch and prevents packet loss. It will report its activity to the MIB Event Generation block for SNMP/RMON MIB accumulations.

SGRAMs Lower Costs

The AL1000 lowers overall system with an architecture that uses SGRAMs (Synchronous Graphic Random Access Memory) to achieve a "no compromise" solution for buffering data. The SGRAMs are low priced because they are a commodity item in high-volume graphics applications. The devices also have the perfect organization (32 bit by 256 Kbit ) for buffering network data.

RoX Bus Provides Scalability

The RoX bus allows an engineer to scale the number of chips to the number of ports in a switch. Each additional AL1000 attached to the RoX bus adds two more Gigabit ports. The RoX bus is also used to relay information to the AL300 Network Management Chip. The RoX bus, which is patent-pending, uses a 32 bit data path running at 75 Mhz. This 2.4 Gbps data rate is effectively doubled to 4.8 Gbps since each chip is simultaneously transmitting and receiving.

AL300 Management Chip

The AL300 uses the RoX bus to collect network management information from the AL1000 devices. The chip manages up to 32 Fast Ethernet ports and provides Spanning Tree Support. It provides all the MIB (Management Information Base) statistics required to support both SNMP (Simple Network Management Protocol) and RMON (Remote Network Monitoring). The device contains on-chip buffers that hold network packets until they are reported to (and from) over a separate bus to an attached CPU.

Availability and Price

The AL1000 is sampling in August with production in October. The chip is priced at $120 in a 352-pin BGA (Ball Grid Array) in quantities of 1,000.

The AL300 management chip is in production now. It is priced at $50 in a 240-pin PQFP (Plastic Quad Flat Pak) in quantities of 1,000.

The AL100 Fast Ethernet chip is in production now. It is priced at $100 in a 352-pin BGA (Ball Grid Array) in quantities of 1,000.

About Allayer

Allayer Communications was founded in 1997 to design, manufacture, market and support semiconductor solutions for high performance network systems. The company provides solutions that give the systems manufacturer advantages in system design flexibility, scalability and cost. Its first product, the AL100 Fast Ethernet Switch IC, enables networking systems OEMs to produce higher performance 100 Mbps Fast Ethernet switches at lower cost. Its AL1000 Gigabit Ethernet Switch IC, brings the same cost and performance advantages to the ultra high speed Gigabit Ethernet switch market.

Allayer resources include important technical and management skills such as expertise in mixed-signal analog/digital semiconductors, bipolar and CMOS technologies, Ethernet and Fiber Optic communications, and network switching systems. The company uses a system solution methodology, rather than a IC-oriented one. Allayer is backed by over $5.5 million in venture funding from Acer Capital America, VenGlobal Capital and others.

The company is headquartered in San Jose, Calif.

Company Contact: Dave Wong Director of Marketing (408) 570-0888 x108 Allayer Communications

Editorial Contact: Curtis Panasuk Principal (650) 594-4800 Curtis & Associates