The designers of next generation embedded systems are continuing pack a wide array of more powerful features into ever smaller and less expensive systems. A key market driver has become the need to integrate high performance 32-bit and 64-bit RISC processors into existing silicon ASIC designs. Adding high performance RISC processing on-chip reduces cost, adds design flexibility, reduces product size and boosts functionality.
MIPS Technologies, Inc. is committed to driving this industry trend by providing its MIPS architecture processors in easily adaptable processor cores. The MIPS Processor Core Roadmap represents the company¹s plan to supply the industry with a variety of design options for obtaining MIPS RISC processor Intellectual Property or IP. Starting in 1999, system OEMs and semiconductor firms can acquire MIPS Technologies, Inc. processor designs in two new ways: optimized and synthesizeable cores. In the future, additional custom cores and embedded CPUs will also be made available for new MIPS processor families.
The new "drop-in" processor cores are designed to be easily adapted for use in a variety of fabrication processes and technologies. This contrasts with previous MIPS cores that were tightly coupled to a given process technology.
The new processor cores are targeted for use by ASIC vendors, fabless semiconductor houses, or original equipment manufacturers (OEMs) who want to combine their existing silicon Intellectual Property with a MIPS Core. For example, a fabless semiconductor company with a network switching interface being produced in a third party foundry, may now combine that switch circuit with an on-chip MIPS core to add functionality and reduce costs.
This market, now being served by other RISC core vendors, was previously not being served by existing MIPS licensees because they can only offer MIPS processor cores as part of a finished ASIC device, fabbed in their own facilities. Now, anyone with ASIC silicon design capabilities can easily add MIPS RISC processors to their products.
The combination of MIPS Technologies, Inc. unique open access Intellectual Property licensing business model and an array of "drop-in" processor cores will ensure that the MIPS processor architecture will maintain and extend its lead in high performance embedded RISC processors.
There are three initial families of MIPS Technologies Processor Core products with product code names of Jade, Opal and Ruby.
TJade processors are high performance 32-bit MIPS RISC processors that are a superset of the highly popular R3000 embedded CPU. It includes many of the higher performance instructions and internal memory management features of the powerful R4300 series 64-bit RISC processors. In addition to standard optimized core and synthesizeable core implementations, an optimized low cost version will also be available.
Opal processors will be pure 64-bit MIPS RISC processors that will be equal in class to the existing R5000 RISC CPUs. Ruby processors will be even higher performance 64-bit RISC processors and will represent the high-end of the embedded MIPS RISC processor family.
In the past, system OEMs could obtain embedded MIPS RISC CPU designs from MIPS Technologies, Inc. and other licensees as mask level IP, or in some cases, as processor cores derived from those embedded CPU designs. The primary focus of prior generations of processor design was at the system level of integration with a clear distinction between fabrication techniques used in the CPU design and those used for the rest of the system. In particular, production processes were tweaked to optimize processor performance in different ways from that used in general ASIC logic.
However, during the mid-1990s, advances in CAD techniques, fabrication processes and silicon foundry capabilities have made possible the integration of processor cores as functional elements in a broader family of standard cell families or as ASIC functional blocks. As a result, more OEMs can take advantage of processor cores provided to them in optimized and synthesizeable formats.
To meet this need, MIPS Technologies, Inc. is expanding its licensing program to include processor cores in both optimized and synthesizeable implementations. Cores available in firm format are specifically tuned to a given process and are provided as physical silicon layout files. Synthesizeable cores are provided at a higher level of abstraction, usually a high level language description of the circuit, and can be quickly adapted to almost any process technology.
Unlike other approaches that require the use of vendor-specific standard cells and fab processes (or extensive design manipulation), the MIPS Technologies, Inc. "drop-in" cores are designed to be easily integrated into a wide range of independent fabrication processes. This means that they can be easily adapted to existing product design flows. These flexible cores enable companies with existing ASIC designs and external foundry relationships to add MIPS RISC processor capabilities without altering their design and fabrication methodologies.
The difference between core formats is determined by the form in which the processor design is delivered to the customer and how that delivery format is created. Previously, processors were designed as separate CPUs (usually available in separate IC packages) and their transfer was at the mask level. OEMs could license the CPU, obtain the mask for the processor they wanted and use it to fabricate ICs. This required that the fabrication processes be nearly identical to the original design process and this restricted useful access to the processor IP.
Synthesizable or synthesizeable cores deliver the processor design in high level language descriptions of the circuit. These high level circuit descriptions can be manipulated by the OEM to implement layouts that fit well with their existing silicon designs and match well to their specific process flow. Synthesizeable cores provide the greatest flexibility, but require the most effort on the part of the customer.
Both custom and optimized cores are delivered as physical layout files that specify the precise silicon geometries for a given process technology. To generate optimized cores, standard ASIC design methodologies like circuit synthesis and automated place-and-routing are used. This tailors a given design to a process technology using the physical parameters of that process. The key advantage of optimized cores is that any design can be quickly implemented in a given technology. In addition, a port to a new technology, say from .25 micron to .18 micron levels is fast, relatively easy and can take full advantage of any new process capabilities without requiring any circuit redesign.
Custom cores are also delivered as physical layout files, but they are generated using manual or custom CPU design methodologies. This requires extensive hand-crafting of the design and manual place-and-routing of circuit elements. This achieves the highest level of performance from a given process technology, but requires much more design effort and offers much less flexibility in porting to other processes.
The new Jade core is a high performance, low-power, 32-bit MIPS RISC core that implements the MIPS instruction set architecture, with enhancements such as the R4000 TLB and privilege-mode extensions. This processor core is compatible with the widely supported R3000 and R4000 (in 32-bit mode) the defacto standards in the embedded RISC processor market.
The core is available in both optimized and synthesizeable versions, making it process-portable. The core includes integrated instruction and data caches. The standard caches are 8KB each, but they can optionally be configured in 2, 4, 6, 8, 12, or 16KB sizes. The 5-stage pipeline supports three execution units (integer, multiply-divide, and branch/load/store). The memory management unit (MMU) has a 32-entry TLB. The 32-byte write buffer supports byte-merging.
Most instructions are executed in a single cycle. The multiply-divide unit (MDU), for example, executes 16-bit x 16-bit multiply-accumulate (MAC) instructions in a single cycle, allowing execution of DSP algorithms, such as software modems.
Power consumption is minimized by the core¹s fully static design, selectable core and bus-interface operating frequency, and two power modes. Cost is minimized by the core¹s small die size. In a typical 0.25um process, the entire core‹with 8KB instruction cache, 8KB data cache, MMU and bus interface‹is less than12 mm2.
Jade cores provide all of the advantages of the popular R3000/R4000 architecture with its large number of development and debug tools in a flexible, low-power, and easy to implement manner. <
The MIPS architecture has achieved an enviable position as the number one high performance embedded RISC processor. It leads the market in units shipped, in breadth and diversity of high-profile applications utilizing the MIPS architecture, and in the number of implementations and configurations from the many MIPS processor licensees.
Nearly 50 million MIPS RISC processors were shipped in 1997 making it the world¹s leading embedded RISC processor architecture with nearly two times more volume than its nearest RISC competitor. MIPS RISC processors are embedded in such high profile systems as the Web TV® Internet appliance, the EchoStar® DISH Network® DBS TV programming system, the Nintendo® 64 and Sony® Playstation® game consoles, the Philips® Velo® handheld PC and the Nino® palmsized PC, the Toshiba® GENIO pocket communicator, the Casio® Cassiopeia E-10 Windows CE-based Handheld PC, the Hewlett-Packard® LaserJet 4000 printers and the Cisco® 8800 Series network switching systems, among many others.
There are more MIPS processors standard product configurations than any other comparable RISC or CISC product. In addition, there are more independent chip-level design teams working on new MIPS processor configurations than for any other architecture. Finally, there are more than 60 independent third-party development tool vendors with high performance development tools supporting the MIPS architecture.
Because of robust performance, breadth of products and depth of support, the MIPS RISC processor architecture has become the market leader in high performance embedded 32-bit and 64-bit RISC processors. MIPS Technologies, Inc. is now extending that leadership with a new family processor cores.
Jade, Opal and Ruby processor core families give system OEMs, ASIC vendors, and fabless semiconductor firms a more flexible option for integrating powerful MIPS processors into their own ASICs. Unlike other approaches that require the use of vendor-specific standard cells and fab processes, the new MIPS Technologies, Inc. cores are designed to be easily adapted to a wide range of independent fabrication processes. This means that they can be easily adapted to existing product design flows. These flexible cores enable companies with existing ASIC designs and external foundry relationships to add MIPS processor capabilities without altering their design and fabrication methodologies.
Constance Sweeney
(650) 567-5059
email: email: cks@mips.com